The present invention relates generally to scan-based testing of integrated circuits, printed circuit boards, and systems, and more particularly to a method and apparatus for accessing multiple such electronic circuits within a system and for optimized testing of multiple such electronic circuits in parallel.
Scan-based testing is frequently employed during the development and manufacturing of electronic components (e.g., Integrated Circuits (ICs)) and systems (e.g., Printed Circuit Boards (PCBs) and Systems On a Chip (SoC) for detecting and diagnosing defects and for debugging. This test method is commonly referred to as “scan” because the state elements of the circuits are configured to form a serial shift (i.e., scan) register, often called a scan path or scan chain, during a test mode of operation. Scan test typically involves serially shifting data into (scan-in) and out of (scan-out) the scan path(s) of a Unit Under Test (UUT) as a way of applying digital logic values as test stimulus and capturing digital logic values in response to the test stimulus. The responses are normally compared against expected scan out data, and any failure during the data comparison generally indicates detection of a defect in the UUT. Thus, for a digital circuit, the scan test mode provides full controllability and observability of inputs and outputs of combinational logic included in the UUT. This greatly simplifies the test problem and provides for high quality tests with overall reduced costs.
Providing serial scan access enables “visibility” into a UUT for test and debug purposes by providing a way of observing/controlling the circuit states without the need for physical probing. Without scan, internal nodes of the circuit would only be accessible through the physical pins of the UUT. In this case, any testing or debugging of the circuit would require applying complex sequences of operations to provide control/observation of the internal states. A UUT with scan can also be used to access other circuits connected to the UUT, e.g., circuits embedded within the UUT such as embedded memories and cores or other circuits connected externally to the UUT. This approach is often employed to access external memories for the purpose of programming their contents, e.g., programming FLASH memory from the Boundary Scan path of an IC connected to the FLASH memory.
Scan access is typically performed in accordance with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture specification, which is incorporated herein by reference. This standard was developed primarily to solve the problems of PCB testing. The IEEE 1149.1 Standard utilizes a Boundary Scan path to facilitate access to the I/O pins of devices mounted on the PCB. In addition, the IEEE 1149.1 Standard can be used to access scan paths within an IC to facilitate test, debug, and in-system configuration of ICs, PCBs, and systems.
FIG. 1 illustrates the conventional IEEE 1149.1 Boundary Scan Architecture 100. As shown in FIG. 1, an IC compliant with the IEEE 1149.1 Boundary Scan Architecture 100 has four (optionally, five) additional component pins called Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO) (and optionally Test Reset (TRSTN)). These dedicated test pins are commonly referred to as the Test Access Port (TAP). Additionally, IEEE 1149.1 compliant ICs implement three scan registers—an Instruction Register (IR) 102 and two standard Data Registers (DRs) called a Bypass Register 104 and a Boundary Scan Register (BSR) 106. FIG. 1 also shows a User DR 108, which the IEEE 1149.1 Standard permits designers to implement to support additional test and debug features in the architecture 100 such as internal scan paths and Built-In Self-Test (BIST).
In the IEEE 1149.1 Standard, the five TAP pins have the following functions:
TCK is an input signal that is provided to synchronize the execution of various test actions, both within the individual IC components and among multiple IC components being accessed through the TAP. TCK is a periodic clock signal, which is generally free running with a constant frequency. However, TCK may be started or stopped, or its frequency may be changed, depending on the application. Most test actions take place on the rising-edge of the TCK pulse but certain actions occur only on the falling-edge of TCK.
TMS is an input pin that is used to control the internal state of a TAP Controller 110 (see FIG. 1). The TAP Controller 110 is a 16-state Finite State Machine (FSM) that provides a standard IEEE 1149.1 protocol for accessing functions within the architecture 100. Certain actions defined by the IEEE 1149.1 Standard are permitted, and can be executed, only in specific TAP Controller states. TMS values are sampled on the rising-edge of TCK.
TRSTN is an input signal that provides asynchronous reset of the TAP Controller 110, which brings it into the Test-Logic-Reset state to allow the IC component to execute its mission function. Regardless of the state of the TCK and TMS inputs, the target TAP Controller enters and remains in the Test-Logic-Reset state as long as TRSTN is at a logic value of 0. Since it is also possible to reset the TAP Controller 110 by setting TMS to the logic 1 value for at least 5 TCK periods, TRSTN has been defined as an optional input signal.
TDI is an input signal that provides serial scan-in data to the device. TDI receives test data from another device's TDO, or from an external test resource such as a scan controller or Automatic Test Equipment (ATE). The logic value of the signal on TDI is sampled on the rising-edge of TCK.
TDO is the serial scan-out from the device. When a device is enabled to scan data, its TDO transmits test data to another device's TDO, or back to the test apparatus. Scan-out values on the TDO output change with the falling-edge of TCK.
The IEEE 1149.1 Standard facilitates connecting the TAP ports of multiple components together to form an IEEE 1149.1 bus, which allows the connected circuits to be accessed with a common TAP protocol. This is typically achieved by connecting the serial data terminals, TDI and TDO, of the individual devices in a daisy chain fashion such that the TDO output from the previous device along the chain is connected to the TDI input of the next device in the chain. Then, by connecting all of the individual TMS, TCK (and optionally TRSTN) signals of the devices in common, an overall TAP bus is formed.
A typical daisy chained configuration 200 of the IEEE 1149.1 bus is depicted in FIG. 2. As shown in FIG. 2, the TDI input on a first device 202.1 (UUT1) and the TDO output on a last device 202.n (UUTn) are used as the serial data input and serial data output of the bus, respectively. Given the bussed configuration 200 shown in FIG. 2, the test apparatus can connect to the TDI, TDO, TMS, TCK and TRSTN of the bus and communicate with the devices 202.1–202.n using the IEEE 1149.1 TAP protocol.
The daisy chained configuration 200 of FIG. 2 can be used on a single PCB. However, a different approach is often used when the TAP bus is extended across multiple PCBs on a system backplane. In this case, implementing the daisy chained TDI/TDO configuration 200 of FIG. 2 along the backplane may be impractical because the scan chain would be disconnected if any board is unplugged. In addition, the overall configuration (e.g., the total length of the scan chain) may change as different types of boards are added or removed. This makes it difficult for the test apparatus to communicate with the individual boards so that they may be properly identified and tested. Consequently, the complexity of implementing a single serial chain across a system backplane has led to the development and use of a configuration of the IEEE 1149.1 TAP bus commonly referred to as the multi-drop bus architecture.
As shown in FIG. 3, a conventional multi-drop configuration 300 of the IEEE 1149.1 bus can be used to provide a single TAP bus across a backplane to allow each board 302.1–302.n to make connections to the same set of wires on the bus, i.e., in parallel. Because TCK, TMS, TDI and the optional TRSTN are input signals, they can be connected across the system backplane to each of the TAPs of the individual boards 302.1–302.n directly. However, care is taken to prevent signal clashes that may result due to connecting the multiple TDO outputs onto the single TDO wire of the multi-drop bus. This is possible as the IEEE 1149.1 Standard requires that the TDO output shall drive out only when serial data is being shifted into/out of the TAP's TDI-TDO pins. This is controlled by the internal states of the TAP Controller 110 (see FIG. 1) so that serial-shift is enabled only during the Shift-IR or the Shift-DR states of the TAP FSM. At all other times, the TDO output is disabled by forcing it into an inactive or high-impedance state.
However, when using the multi-drop configuration 300, all TAP Controllers receive the same set of input signals and therefore operate in lock step with each other. That is, all of the TAP Controller's FSMs are in the same state such that, unless certain changes are made to the architecture, enabling the TDO output from any TAP Controller (e.g., during the Shift-DR state) also enables the TDO output from all other TAP Controllers. In addition, because all TAP Controllers operate in lock step and receive the same input data values (i.e., from the commonly bussed TDI), it is difficult to perform different test actions on the different boards 302.1–302.n without special consideration in the architecture.
Controlling the multi-drop configuration 300 of the IEEE 1149.1 bus usually requires the use of a customized version of the TAP controller and a special protocol to communicate with it. Further, the TAP controller and protocol is generally used with each device or board that interfaces to the multi-drop bus. The multi-drop configuration 300 necessitates the ability to address the TAP controllers on the bus so that a single TAP controller drives its TDO output only after it has been uniquely selected. When unselected, the TAP controllers still receive the TDI input and operate in lock step, but do not enable their TDO outputs to drive onto the multi-drop bus.
Current solutions for parallel testing or configuration of programmable circuits include employing a “ganged access” or “scan multiplier” configuration of the UUTs. A conventional ganged access scan multiplier configuration 400 using the IEEE 1149.1 bus is shown in FIG. 4. With this configuration, inputs to UUTs 402.1–402.n (i.e., TDI, TMS, TCK and TRSTN) are bussed in parallel, while scan outputs from each UUT 402.1–402.n (i.e., TDO) are individually connected to a multiplexing controller 408. Thus, a dedicated TDO line for each UUT 402.1–402.n on the bus is generally required. For applications that require a high degree of parallel testing, this would require a large number of TDO signals connected from the UUTs 402.1–402.n back to the multiplexing controller 408. So, for example, if it is desired to connect one hundred UUTs in this configuration 400, one hundred separate TDO lines (one per UUT) would be routed back to a TDO select circuit 406. The purpose of the multiplexing controller 408 is to allow a simple interface with a general-purpose IEEE 1149.1 controller 404 having just the 4 or 5 standard TAP controller pins, as shown in FIG. 4.
With the approach of the ganged access scan multiplier configuration 400, the IEEE 1149.1 controller 404 provides the TAP protocol to all UUTs 402.1–402.n in parallel, and therefore all UUTs 402.1–402.n receive the same TAP instructions and test data. Further, as shown in FIG. 4, the multiplexing controller 408 can only select a single TDO output from one of the UUTs to connect back to the IEEE 1149.1 controller 404. Thus, the gang access scan multiplier configuration 400 can send scan-in test data on the common TDI of the bus to all of the UUTs 402.1–402.n in parallel, but receives scan-out test data on TDO from only one UUT at a time. This approach may reduce the time required to program multiple devices, however it does not speed up operations that require checking the scan-out test data from the TDO outputs of the respective UUTs. So, for example, verifying the programmed contents of FLASH memories on the UUTs would require reading back and checking the contents of each FLASH memory individually, i.e., one at a time. Any other operations that require polling or checking status suffer a similar penalty. For testing purposes, the TDO scan out is checked on each UUT for each bit of scan out. So, clearly there is little advantage to this approach over serial testing of the UUTs. Accordingly, the conventional gang access scan multiplier configuration 400 is not an optimal solution for parallel testing.
The use of Design For Testability (DFT) techniques by engineers—including implementation of IEEE 1149.1 Boundary Scan, internal scan, and Built-In Self-Test (BIST)—has increased considerably as ICs, PCBs, and systems have become more complex. This increased use of DFT has provided for high quality tests, reduced test times and test costs, reduced debug effort, and reduced time to market. However, as electronic circuits continue to grow in complexity, test continues to be a challenge and may become a major bottleneck in the design and manufacture of high technology electronic systems. Examples of technologies that are contributing to increased design complexity and therefore must be dealt with during test and debug, include embedded cores, embedded memory, analog/mixed-signal applications, and In-System Configuration (ISC) of programmable logic (e.g., CPLDs and FPGAs) and nonvolatile memories (e.g., FLASH memories). Further, a growing market demand for such products, in addition to increased competition in the market place, continue to place pressure on manufacturers of electronic systems to reduce costs and improve time to market. Thus, new methodologies that both reduce costs and minimize the time required for testing, debugging, and configuration of complex ICs, PCBs, and systems are needed.